The present invention relates to an erase method in a non-volatile memory device. More particularly, the present invention relates to a method of testing a non-volatile memory device for enhancing threshold voltage distribution characteristics after an erase operation is performed for a multi level cell (MLC) memory device.
Generally, a flash memory device as a non-volatile memory device is divided into a NAND flash memory device and a NOR flash memory device.
In the NOR flash memory, each of the memory cells are connected independently to a bit line and a word line, and so the NOR flash memory has excellent random access time. Whereas, in the NAND flash memory, only one contact is required for one cell string because memory cells are connected in series, and so the NAND flash memory has excellent characteristics for integration. Accordingly, the NAND flash memory has been generally employed in high density flash memory.
The well-known NAND flash memory device includes a memory cell array, a row decoder and a page buffer.
The memory cell array has word lines disposed along rows, bit lines disposed along columns, and cell strings corresponding to each of the bit lines.
Recently, multi bit cells for storing a plurality of data bits in one memory cell has been actively studied so as to increase the degree of integration of the above flash memory. This memory cell is referred to as a multi level cell (hereinafter, referred to as “MLC”). A memory cell for storing one data bit is referred to as a single level cell (SLC).
The MLC has a plurality of threshold voltage distributions so as to store a plurality of data. This means that the possible data values are stored differently in accordance with each of the cell distribution voltages.
The flash memory device is manufactured on a wafer. Here, a memory cell having a fail, i.e. a failed memory cell in accordance with a test process is masked on the wafer, and then a repair process is performed about the failed memory cell by using a laser.
FIG. 1 is a flow chart illustrating a common process of testing a memory cell on a wafer.
In FIG. 1, in the case that a test is started on the wafer, a power source test, for verifying whether or not a power source is normally applied to each of memory chips, is performed in step S101.
In step S103, every memory cell on the wafer is erased when the power source test is finished. The memory cells on the wafer may have different threshold voltages during a manufacturing process. Accordingly, every memory cell is erased so that the memory cells have threshold voltages of less than 0V.
In step S105, a hard erase verify is performed so as to verify whether or not every memory cell has a threshold voltage of less than 0V in accordance with the above erase process.
In the case that a fail has occurred to a specific memory cell in accordance with results of the hard erase verify in step S107, the test operation is stopped in step S109.
In step S111, data in the failed memory cell are read, and information related to the read data is stored in a corresponding page buffer.
In step S113, a failed page buffer is determined in accordance with the stored information, masking data are inputted to the page buffer connected to the memory cell so that a latch in the failed page buffer outputs a pass signal in a following operation.
In step S115, every memory cell is erased again after the masking data are inputted to the page buffer, and then it is verified whether or not the masking is normally performed through the hard erase verify. Generally, since the masking is normally performed in the steps S111 and S113, the hard erase verify is passed.
In step S117, a soft program is performed so that the memory cells have a threshold voltage near 0V in the case that the hard erase verify is finished. Particularly, in the case that the threshold voltage of the memory cell is much smaller than 0V when programming the memory cell, a programming time is long and the memory cell may affect other memory cells. Accordingly, the memory cells are pre-programmed so that the memory cells have a threshold voltage near 0V.
In step S119, verifying the soft program is performed by using a soft verify voltage SEV.
As described above, in the case that a failed memory cell has occurred during the test process, the test process is stopped, the information concerning the failed memory cell is stored, and masking is performed about the failed memory cell. Then, every memory cell is erased, and the hard erase verify is performed. As a result, a test time becomes longer.
FIG. 2A to FIG. 2C are views illustrating the threshold voltage shifts of the memory cells in accordance with the operation in FIG. 1.
The memory cells on a wafer may have various threshold voltages at an initial time. In FIG. 2A, every memory cell is erased in step S103 so that the memory cells have a threshold voltage of less than 0V. Here, the hard erase verify is performed by using a hard verify voltage EV.
FIG. 2A to FIG. 2C show a process of shifting the threshold voltages of the memory cells having a wide threshold voltage distribution so that the memory cells can have a narrow threshold voltage distribution near 0V.
In FIG. 2B and FIG. 2C, the soft program is performed so that the memory cells have threshold voltages near 0V. Then, a verify is performed by using the soft verify voltage SEV to determine if the memory cells threshold voltages near the soft verifying voltage SEV.
In the case where the process of erasing every memory cell and the hard erase verify are performed in the test process, a failed memory cell usually occurs. Hence, a process of inputting the masking data to corresponding page buffer is required before following the soft program and the verify process are performed so that the hard verify is passed. Accordingly, a time for testing the wafer is increased due to the process of inputting the masking data.